Design of 7T SRAM using InGaAs-Dual Pocket-Dual Gate-Tunnel FET for IoT applications

The Internet of Things (IoT) is becoming increasingly popular in areas like wearable communication devices, biomedical and home automation systems. IoT-compatible processors or devices need larger integrated memory circuits, static random access (SRAM). design such a with fast times low leakage challenge. In this article, we have proposed 7T SRAM cell using an InGaAs-dual pocket-dual gate-tunnel FET (InGaAs-DP-DG-TFET) device. We compared the key metrics SRAM, as read/write delay, stability, power consumption, based on existing TFET devices. designed work significantly improved read write times. shows decrement delay (write delay) by approximately 10x (210x) 2.5x (43x) to implemented Si-DP-DG-TFET InGaAs/Si-DP-DG-TFET at Vdd = 700 mV. has highest margin (WM) least amount other cells examined here. WM 5x 1.6x higher 500 mV, counterparts, respectively. computed since it essential factor SRAM. To explore performance TFET-based operation, carried out circuit simulations various supply voltages for different sizes. These also offered assessment cell’s dynamic performance. employed Verilog-A-based look-up-table technique ran commercial HSPICE simulator. make promising candidate IoT applications.